1. Field of the Invention
The invention relates generally to semiconductor structures that may include metal oxide semiconductor field effect transistor (MOSFET) devices. More particularly, the invention relates to semiconductor structures with enhanced performance.
2. Description of the Related Art
As MOSFET device dimensions decrease, and in particular as MOSFET gate electrode dimensions decrease, several novel effects become more prominent within MOSFET devices. Particularly detrimental novel effects are short channel effects. Short channel effects result from an inadequate level of electrical control of a gate electrode over a channel region within a MOSFET. Undesirable results of short channel effects include high MOSFET off-state currents, high standby power consumptions, and detrimental electrical parameter variations within MOSFET devices.
In an effort to minimize short channel effects and reduce variation of threshold voltage, MOSFET devices have recently been fabricated with undoped and extremely thin body regions, including undoped and extremely thin channel regions. However, while these undoped body regions provide MOSFET devices with enhanced short channel effect control, undoped body regions may in fact provide for compromise of other electrical parameters of MOSFET devices.
Various semiconductor structures having enhanced performance, and methods for fabrication thereof, are known in the semiconductor fabrication art.
Specific examples of such semiconductor structures are disclosed by: (1) Kedzierski et al., in “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEDM Technical Digest, pp. 247-50, 2002 (metal gate FinFET and fully depleted SOI devices with enhanced electrical performance); (2) Krivokapic et al., in “Locally Strained Ultra-Thin Channel 25 nm Narrow FDSOI Devices with Metal Gate and Mesa Isolation,” IEDM Technical Digest, 2003 (NMOS & PMOS devices fabricated within a semiconductor on insulator (SOI) substrate for enhanced performance); (3) Kedzierski et al., in “Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation With Ni,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2115-20, 2004 (metal gate FinFETs fabricated with enhanced workfunction control); and (4) Doris et al., in “High Performance FDSOI CMOS Technology with Metal Gate and High-K,” 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 214-15, 2005 (CMOS devices with workfunction tuning for enhanced performance).
Semiconductor structure performance requirements are certain to increase as semiconductor structure and device dimensions decrease. Thus, desirable are semiconductor structures, and methods for fabrication thereof, that provide enhanced performance at decreased dimensions.